This invention pertains in general to large scale integrated (LSI) circuits and in particular to binary adders used in such circuits.
As is known, a binary adder is one of the basic building blocks of a digital computer, so the speed at which a binary adder may be operated directly affects the speed of a digital computer. It is of particular importance that the speed of a binary adder be maximized for use in LSI circuits. A relatively high speed full adder using the well-known CMOS technology, as described in an article entitled "LSI's for Digital Signal Processing" by N. Ohwada, T. Kimura and M. Doken, IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 2, April 1979, pp. 214-220, incorporates an exclusive-OR type adder in combination with transfer gates. The addition of the transfer gates increases the speed of operation significantly as compared to a conventional full adder using only exclusive-OR gates. Unfortunately, however, there is a logic delay associated with developing the requisite carry output signal. That is to say, the transfer gates that develop carry output signals are controlled by either A.sym.B or .circle.A .sym.B logic signals (where A and B are the signals to be added) so the delay inherent in developing either one of such logic signals limits the speed of operation.